The present invention relates to ferroelectric memories, and more specifically to a circuit and method for increasing the signal margin of small 2T/2C ferroelectric memories in order to improve retention.
In existing 2T/2C FRAM® structures, the same load capacitances are designated to all of the bit lines. For large array size memory, parasitic capacitances contribute most of the bit line loads and all the bit lines have almost equal capacitive loads. However, for small 2T/2C FRAM memories, the parasitic capacitances on the bit lines are not large enough and extra capacitors are added to the bit lines to optimize the signal margin during a read operation. One of the existing techniques for increasing signal margin is to add linear ferroelectric capacitors to the bit lines to save area and to balance the capacitance load between a bit line (BL) and its complementary bit line (BLB). Since the dielectric constant of ferroelectric materials is much higher than that of silicon dioxide, the capacitor size using ferroelectric materials is much smaller than conventional capacitors using silicon dioxide.
The problem with this existing solution is that it does not fully exploit the advantage of using ferroelectric capacitors. What is desired is a circuit and method for increasing the signal margin of small array ferroelectric memories, while overcoming the problems associated with prior art solutions and also fully realizing the potential of using ferroelectric capacitors.